module DISPARITY	(
							input wire	iSRAM_CLK,
							input wire	iDISP_CLK,
							input wire	iRST_N,
//--Read Port 2
							input wire	r_address2,
							output wire	r_stop2,
							input wire	r_data2,
							input wire	r_data_avai2,
//--Read Port 3
							input wire	r_address3,
							output wire	r_stop3,
							input wire	r_data3,
							input wire	r_data_avai3,
//--Write Port 7
							output wire	w_address7,
							output wire	w_stop7,
							output wire	w_data7,
							output wire	w_BE_N7,
							output wire	w_port_avai7,
							input wire	SW
);


assign r_stop2 =1;
assign r_stop3 =1;
assign w_stop7 =1;



reg	 [1:0]	pre_byte_no0, byte_no0;
always @(posedge iDISP_CLK or negedge iRST_N)begin
	if (!iRST_N)begin
		byte_no0 	<= 2'b00;
//		pre_byte_no0<=2'b11;
	end
	else begin
			byte_no0	<=	byte_no0 + 2'b01;
			case (byte_no0)
				2'b00: DATA_L_8_2	<=	DATA_L_32[23:16];
				2'b01: DATA_L_8_2	<=	DATA_L_32[31:24];
				2'b10: DATA_L_8_2	<=	DATA_L_32[7:0];
				2'b11: DATA_L_8_2	<=	DATA_L_32[15:8];
			endcase
	end
end
reg rinc2;
always @ (posedge iDISP_CLK) begin
	pre_byte_no0 <= byte_no0;
	if ((byte_no0 == 2'b00)&&(pre_byte_no0 == 2'b11))
		rinc2 <= 1;
	else
		rinc2 <= 0;
	end

fifo1	DISP_FIFO_L (	.rdata(DATA_L_32),
						.wfull(r_stop2),
						.rempty(),
						.wdata(r_data2),
						.winc(r_data_avai2), .wclk(iSRAM_CLK), .wrst_n(1'b1),//oRequest
						.rinc(rinc2), .rclk(iDISP_CLK), .rrst_n(1'b1)//oRequest
				 );	

Line_Buffer 	u0	(	.clken(1'b1),
						.clock(iDISP_CLK),
						.shiftin(DATA_L_8_2),
						.taps0x(DATA_L_8_1),
						.taps1x(DATA_L_8_0)	);

reg [7:0] 	L10,L11,L12,
			L20,L21,L22,
			L30,L31,L32
endmodule